1. Field of the Invention
The present invention relates to a circuit for the detection of an open load for a vertical power MOS transistor, and more particularly relates to so-called "Smart Power" circuits that include on a single semi-conductor chip, one power MOS transistor and logic components.
2. Discussion of the Related Art
In the case of MOS transistors operating in switching mode (that is, in a cut off state or in a fully conductive state) and connected to a variable load, for example a load comprised of several loads in parallel, some of which are selectively selected, it is useful for the user to know whether a load is open. In this case, even if the power transistor is set conductive, it does not conduct any current.
It is also noted that a vertical power MOS (VDMOS) transistor includes numerous cells disposed in parallel and has a common drain terminal that is formed by the rear side of the silicon chip. On the other hand, the source or gate terminals, respectively, of the VDMOS transistors can be interconnected or connected by subgroups.
FIG. 1 schematically represents a conventional open load detection circuit. The drain of a power MOS transistor TP is connected to a high supply voltage terminal VCC and its source to a load L that has its second terminal connected to a low supply voltage terminal, generally to ground. A detection transistor TS, comprised of a small number of cells that are identical to the cells of the main transistor, is also connected by its drain to the supply terminal VCC. The source of transistor TS is connected to ground through a reference current source IREF. The gate of transistor TS is connected to the gate of transistor TP and is fed by a control voltage VG. The voltages VL and VS on the source terminals of transistors TP and TS are compared in a comparator C1 that provides an alarm signal OL when the source voltage of transistor TP becomes lower than the source voltage of transistor TS, that is, when current IL in the load becomes lower than a threshold current IL.sub.0.
In a first approximation, considering that the power transistor TP includes N.sub.p cells (for example, 5,000 to 20,000) and that the detection transistor TS includes N.sub.s cells (for example, 10 to 25), the threshold current IL.sub.0 is defined by the relation
IL.sub.0 =(N.sub.p /N.sub.s)IREF.
Thus, theoretically, if IREF is selected sufficiently low, the detection threshold can be very low. Indeed, it is generally desirable that this threshold be very low in order to differentiate the case when the charging current is low because the load has a high value from the case when the current is low, or zero because the load is open (disconnected or damaged).
In practice, comparator CI, that is integrated in the chip that contains the power component, may have a non-negligible offset voltage, for example, between -2 and +2 mV. This offset voltage is hereinafter referenced "Voff" Hence, the minimum value that can be reliably detected between the source voltages VL and VS of transistors TP and TS is: EQU VL-VS=Voff. (1)
with IL being the current in the load, RonP, the resistance in the conductive state of the power transistor TP, and RonS, the resistance in the conductive state of the detection transistor TS, one can write EQU VL=VCC-RonP.IL.sub.0 EQU VS=VCC-RonS.IREF.
Equation (1) is then: EQU -RonP.IL.sub.0 +RonS.IREF=Voff (2)
whereby EQU IL.sub.0 =(RonS/RonP)IREF-Voff/RonP
since RonS/RonP=N.sub.p /N.sub.s, the following equation is obtained: EQU IL.sub.0 =(N.sub.p /N.sub.s)IREF-Voff/RonP. (3)
It necessarily follows that (N.sub.p /N.sub.s)IREF must be higher than Voff/RonP; therefore the lower limit of IL is: EQU IL.sub.0 =2Voff/RonP. (4)
Thus, the minimum detection threshold is reversely proportional to the resistance value in the conductive state of the power MOS transistor TP. By way of example, if RonP=0.05 ohm and Voff=2 millivolts, the minimum current threshold IL.sub.0 is 80 mA. Such a value is too high in numerous practical applications when it is desirable that this threshold be approximately 10 mA.
To solve this problem, circuits servocontrolling the gate voltage of a power MOS transistor with respect to the voltage drop across this transistor, through a linear regulation loop, are provided in the prior art. Such a method avoids some of the problems of the above described circuit because the detection threshold becomes independent of the resistance during the conductive state of the power MOS transistor and is very slightly sensitive to the offset voltage of a detection comparator. A problem with the above described method is the drawback associated with the provision of a more complex circuit and the drawback inherent in any linear regulation, i.e., a possible instability of the servo-control loop. Indeed, in the case of an inductive load, voltage oscillations in the load may occur during the switching on. Similarly, in the case of a capacitive load, the switching off of the load may cause the gate voltage to oscillate.
Thus, in order to provide a signal for detecting open loads, the prior art suggests either a solution such as the one shown in FIG. 1, that is simple and reliable but with unavoidably a relatively high detection threshold, or a solution that is relatively sensitive but complex and possibly unstable.